To support the increased graphics requirements and I/O bandwidth, the Intel 925x Express chipset incorporates a new memory controller hub backbone architecture. This new design includes wider internal data buses that support dual channel DDR2 memory technology at 533mhz or up to 8.53 GB of peak memory bandwidth for improved platform performance. The new architecture also supports both asynchronous and true isochronous data traffic with dedicated internal pipelines and specialised arbitration.

Micron supply the memory in this test setup, 2 x 512 boards of DDR2. Microns new DDR2-533 SDRAM is 1.8v VDD and SSTL-18 I/O. Micron are shipping modules in 256megabyte, 512 megabyte and 1 gigabyte densities.

This new technology is on a 64 bit memory system and can handle around 4,300 megabytes of data per second which is more than 1.5 times faster than standard DDR333.

For additional DDR2 SDRAM resources head over to www.micron.com/ddr2

• VDD = 1.8V, VDDQ= 1.8V
• I/O = SSTL_18
• 200mhz and 266 mhz clock frequencies
• 400 Mb/s/pin and 533 MB/s/pin data rates
• 3,200MB/s and 4,300 MB/s for 64 bit systems
• 4n data prefetch
• 4 banks for 256 MB and 512 MB devices
• 8 banks for 1 gb devices
• Burst Length of 4 or 8
• WRITE latency = READ latency = 1 clock
• Differential data strobe option
• Duplicate RDQS data strobe option on x8 configurations
• CAS Latency: 3 and 4 clocks
• Posted CAS# additive latency: 0,1,2,3 and 4 clocks
• On-die termination (ODT)
• "Lead-free" FBGA packaging

 

 

Next: X600XT

 

Select 1. Intro/EE/motherboard 2. The Bios 3. DDR2 4. X600XT 5. Test Setup 6. PCMark02 7. PCMark 04 8. Sandra 2004 9. Aquamark 3 10. DH Photoshop Bench 11. Farcry 12. Colin McRae 4 13. Painkiller 14. ATI Overclocking 15. Conclusion