Intel’s Tukwila Confirmed to be Quad Core

Iria · May 6, 2006, 11:34 PM

Source: RealWorldTechnologies
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Paul DeMone, an eminently respected industry observer at Real World Technologies has dug up some information on Tukwila, the next generation microprocessor in the Itanium family.

According to several slides at an HPC conference in Asia, Tukwila will be a quad core part, confirming earlier rumors reported by Ashlee Vance of the Register and Charlie Demerjian of the Inquirer. Tukwila features an on-die FB-DIMM memory controller, which will lower access latency. The FB-DIMM controller likely supports 4 channels of memory, possibly more. As a result of the lower memory latency, Tukwila requires less cache than its predecessor. Montecito featured 27MB of cache, for two processors, while Tukwila is reported to have 6MB of L3 cache per core, or 24MB for each MPU. Preliminary diagrams also indicate that there is on-die switch for traffic between the four cores and caches on each chip.

May 6, 2006, 11:34 PM	#1
Iria DriverHeaven Extreme Member Join Date: Apr 2004 Posts: 7,275 Rep Power: 74	Intel’s Tukwila Confirmed to be Quad Core Source: RealWorldTechnologies __________ Paul DeMone, an eminently respected industry observer at Real World Technologies has dug up some information on Tukwila, the next generation microprocessor in the Itanium family. According to several slides at an HPC conference in Asia, Tukwila will be a quad core part, confirming earlier rumors reported by Ashlee Vance of the Register and Charlie Demerjian of the Inquirer. Tukwila features an on-die FB-DIMM memory controller, which will lower access latency. The FB-DIMM controller likely supports 4 channels of memory, possibly more. As a result of the lower memory latency, Tukwila requires less cache than its predecessor. Montecito featured 27MB of cache, for two processors, while Tukwila is reported to have 6MB of L3 cache per core, or 24MB for each MPU. Preliminary diagrams also indicate that there is on-die switch for traffic between the four cores and caches on each chip.