thesis

Hi all!

I have looked at the AD_EXT connector on my Audigy2 board and come to the following conclusions:

• there are four S/PDIF outputs
• there are two S/PDIF inputs (one on the CD connector though)
• there are two I2S inputs

In total, this makes eight digital channels in and eight digital channels out.

Furthemore, the S/PDIF outputs are probably clock-locked (I can't see a good reason to design it otherwise) so only one clock recovery device (like DIR1703) is needed and the rest can be slaved to this device (and use simple logic in a small FPGA for decoding Manchester and re-framing from S/PDIF to I2S). Connect a Wavefront (used to be Alesis Semiconductor) AL1401A to the four recovered streams, delayed (if required) to a common bit clock, a Toslink transmitter (TOTX173 I guess) and you're done. So ADAT output is simple and cheap.

I suppose the ADAT input would be trickier. First, you've got to receive the optical with a TORX173, then demux it by an AL1402. A conversion to S/PDIF for the first four channels is easy (even in general purpose logic). Now, the problem is that the I2S inputs require a slave at the other side. If the Emu10k2 can be slaved to the S/PDIF clock, it's no problem, since all ADAT channels have a common clock, and all that is needed is simple delaying of samples to achieve synchronisation with the I2S sample sync signal. However, if the Emu10k2 is persistent in keeping its own clock, it's very bad, because resampling will be needed and it's not like it's easy, because the two clocks will be very close and will probably float with temperature .

I've got all the chips lying around in here, so it's a matter of designing a PCB and the FPGA logic for standard conversion and retiming.

How do you think, does it make sense? I don't know a lot about Emu10k (although I do know a bit about ADAT - I have done some experiments with my SGI Octane which has ADAT built in and with the Alesis chips, too - I'm writing a reverse-engineered audio driver for it so I need some ADAT reference). BTW. This is a good audio implementation, you can slave any clock to any clock in it.

Nappylady

(Travelrec will know a *LOT* more than me on this topic, but here's a start...)

If you simply plug a SPDIF source into one of the SPDIF pins on AUD_EXT, the EMU10K2 will, by default, resample that SPDIF input to its own 48khz clock on-the-fly. So, there can be a small loss of quality. However, in recent kX driver revisions, something called "SPDIF Bypass" allows you to record one of the SPDIF inputs *without* resampling--but at the moment, it's limited to use with the WinMM recording, so only 2 channels can be recorded at a time.

If alll your sources were guaranteed to be the same clock rate, I can't think of a reason you couldn't SPDIF bypass four channels and I2S four channels (I could be wrong, but I don't think I2S resamples either) and then let Eugene modify the driver to allow bypassed channels to go to ASIO...

I think this is possible! Keep us posted on what happens with it!

thesis

S/PDIF would work, it's clear. Now, the I2S might be a problem.

Who is the master of I2S - in other words, who generates the Frame Sync and Bit Clock (especially the Bit Clock)? Because if it's not the add-on, there *will* be some serious problems with resampling. I looked around a bit and resampling frequencies that are close (47.9998 kHz -> 48.0012 kHz for instance) is pretty impossible.

Of course, the easiest way would be to repeat or drop samples when the clocks slip, but this would be so ugly I'm not having anything like that here...

It is a pity that the card clock can't be slaved to one of the S/PDIFs. I mean, it's not like it's hard, it's just a single PLL to up-convert the input clock to some convenient frequency and a clock multiplexer.

Nappylady

well if you're ambitious enough to make your own PCBs, you probably have a soldering iron that's studly enough you could make your own clock circuits for your card... I think the pins on the 10K2 chip for clock sync and everything are known, and it sounds like you'd know enough to perform the modification...

http://www.electricstart.de/index.htm

Travelrec is, IMO, the most knowledgeable about these things--he's in Germany, so he'll maybe see this thread and reply while we're sleeping tonight.

thesis

Unfortunately the I2S master is really the Emu10k2 chip.

I think there is one crystal on the Audigy2. So it's probably 24.576 MHz for the whole card. I would probably find out which pin is the input, which is the output and solder something to the input. This should allow me to clock the card at will. This is not the end of troubles, though.

The Alesis AL1402 receiver has only a 12.288 MHz output so I'd have to double the frequency.

There is also a question of switching from internal crystal to ADAT and back. After all, we don't want the card to work only if an ADAT input is connected to it, and hang the machine if it isn't. (Which would probably happen.)

This will be a real problem because exceedingly assymetrical clock cycles (which would appear during a switch) can upset digital logic badly, especially if it uses PLLs (which it surely does, to generate the 98.304 MHz core clock). More often than not, the aforementioned logic would have to be reset.

So it would be needed to make a phase-aligned switch (switch from one clock to another when the phase difference between them is small). This is no mean feat, especially if clocks are very close and the phase-alignment seldom happens (as it is the case here - it might never happen, too).

It is possible that a smooth transition between two clocks could be done using a PLL retimer with a long adaptation time. However, PLLs exhibit interesting non-linear properties, which essentially means that we don't know until we test it

dj_stick

the audigy series cards can slave to an external clock

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thesis

Where should I apply this clock?

dj_stick

i'm not sure how… otherwise you could try to use the ac97 clock and halve it

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thesis

No way I can use the AC97 clock. The AL1402 is the ADAT receiver and it's always synchronous to the incoming ADAT clock. It is "emu10k, use my clock or DIE!".

TravelRec.

Hi thesis!

On Audigy 2 cards the I2S seems to be a master device. You´ll get the bitclock from the card. Ask user SAMIR for the complete layout of AD_EXT. He´s the one who figured out the pinout . But all these is not really tested yet. A possible way to do what you want, is to resample that signals before feeding in I2S (i´ve done this for my Audigy1 with a Sample Rate Converter from Crystal: CS8420, very cool S/N performance -112db), this helps to avoid clicking and desyncronizing, due to the locked DSP. BTW: I have 14 input channels with the Audigy 1 (with AC97), with Audigy 2 you can get 12 if you use Philips onboard 2nd A/D and AC97 too.

Greetings!

TravelRec.

__________________
ASUS P4P800-VM P4HT 3.0GHz@800Mhz FSB, 1GB 400Mhz DDR DualChannel, Audigy2ZS with 2 optical SPDIF in, 3 optical SPDIF out, 8 analog mono in, 8 analog out // ASRock P4i65G P4HT 2.4GHz@800Mhz FSB, 1GB DDR DualChannel, Audigy SB0090 with 4 SPDIF in + 4 SPDIF out // Dell OptiPlex GX1+ PIII @ 600 MHz, 384 MB SDRAM, CT4670 with 2 SPDIF in + 2 SPDIF out // Toshiba Libretto 100CT, Audigy2ZSNB SB0530 // MSI MS-6151 PIII @ 450 MHz 384 MB SDRAM, CT 4790 PCI 512 // ATARI 1040 STE, 8Mhz, 4MB RAM, SM124 // ATARI 130XE, XF551, SIO <-> PC interface

thesis

Hi, and thanks for the authoritative reply!

I think that it would be better to slave the board clock to my clock. It would mean better quality, and I think it could be done. What would be needed is to add a retimer after the ADAT clock. This will be a PLL to lock on the input signal. There are two possible realizations:

* a typical VCO-based PLL that would be switched from ADAT clock to internal clock
* a VCXO-based PLL that would be synchronized to ADAT clock or free-running

The first approach is easier, but the second one provides better jitter and other timing properties, too - the ADAT clock is "cleaned" from jitter by the inherently low-jitter VCXO (telecommunications systems tend to use VCXO here-and-there for this very purpose). However, the question of VCXO pullability (they are crystal-based so they don't change a lot even if you want them to) requires some experiments.

TravelRec.

Hi again!

You are on the right way. One reason why I suggested the CS8420 is, that it has 2 different stages: one PLL input stage that has high jitter rejection, and the output stage that can easily read out with soundcard´s clock. Samplerate ratio can vary between 1:3 and 3:1. Chip´s performance is also cool (like I said) and it runs in hardware-mode (without the need of any processor). I think, it´s possible to add two of such devices (one Master, one Slave) on I2S port. Slaving the I2S is not possible - and if you use SRCs there is no need of it.

Greetings!

TravelRec.

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ASUS P4P800-VM P4HT 3.0GHz@800Mhz FSB, 1GB 400Mhz DDR DualChannel, Audigy2ZS with 2 optical SPDIF in, 3 optical SPDIF out, 8 analog mono in, 8 analog out // ASRock P4i65G P4HT 2.4GHz@800Mhz FSB, 1GB DDR DualChannel, Audigy SB0090 with 4 SPDIF in + 4 SPDIF out // Dell OptiPlex GX1+ PIII @ 600 MHz, 384 MB SDRAM, CT4670 with 2 SPDIF in + 2 SPDIF out // Toshiba Libretto 100CT, Audigy2ZSNB SB0530 // MSI MS-6151 PIII @ 450 MHz 384 MB SDRAM, CT 4790 PCI 512 // ATARI 1040 STE, 8Mhz, 4MB RAM, SM124 // ATARI 130XE, XF551, SIO <-> PC interface

thesis

OK, so I'm reclocking the whole card. AFAIR there is one 24.576MHz crystal. If I dike it out and feed the card with my own 24.576MHz (plus or minus a few ppm), I'll have my way without resampling (it wouldn't be bit-accurate; why use ADAT if you are not bit-accurate anyway?).

I think I will use a high-stability TCXO at 100 MHz and clock a AD9850 digital clock synthesizer from it. The clock synth is nice because I can give it a 32-bit word and it gives me the *exact* frequency I wanted. This clock will be lowpass-filtered so no harmonics will come and jitter it around. The output will be fed into the card.

The tuning of the AD9850 will be done using a phase-frequency detector and a small microcontroller (ADuC814 for instance). This should solve the problem of wander. If there is an ADAT input clock, the card will be slowly (at least a few seconds) drift to the ADAT clock, and then phase-lock with it. If there is no ADAT clock, the microcontroller will keep the last used frequency.

TravelRec.

Hi!

Sounds cool, if it is working, please let us know . But don´t burn your card - I don´t know, how the 10k2 will react on false main frequency input (if an error creates higher clocks than specified...). It´s nice to see what people do to get maximum power from their "consumer" sound-cards .

Good luck!

TravelRec.

__________________
ASUS P4P800-VM P4HT 3.0GHz@800Mhz FSB, 1GB 400Mhz DDR DualChannel, Audigy2ZS with 2 optical SPDIF in, 3 optical SPDIF out, 8 analog mono in, 8 analog out // ASRock P4i65G P4HT 2.4GHz@800Mhz FSB, 1GB DDR DualChannel, Audigy SB0090 with 4 SPDIF in + 4 SPDIF out // Dell OptiPlex GX1+ PIII @ 600 MHz, 384 MB SDRAM, CT4670 with 2 SPDIF in + 2 SPDIF out // Toshiba Libretto 100CT, Audigy2ZSNB SB0530 // MSI MS-6151 PIII @ 450 MHz 384 MB SDRAM, CT 4790 PCI 512 // ATARI 1040 STE, 8Mhz, 4MB RAM, SM124 // ATARI 130XE, XF551, SIO <-> PC interface

Samir

thesis:

Maybe this info might help you.... It shows how clock crystal is connected to the rest of the card trought p16v chip which seems to control other chip's clocks...

http://www.bih.net.ba/~info.com/Audi...ngineering.gif

Keep up the good work & keep us posted about your progres...

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MU3NKA 3A HAPO6!