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Old Aug 26, 2004, 02:21 AM   #1
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Cool! Adding ADAT support to Audigy2

Hi all!

I have looked at the AD_EXT connector on my Audigy2 board and come to the following conclusions:
  • there are four S/PDIF outputs
  • there are two S/PDIF inputs (one on the CD connector though)
  • there are two I2S inputs

In total, this makes eight digital channels in and eight digital channels out.

Furthemore, the S/PDIF outputs are probably clock-locked (I can't see a good reason to design it otherwise) so only one clock recovery device (like DIR1703) is needed and the rest can be slaved to this device (and use simple logic in a small FPGA for decoding Manchester and re-framing from S/PDIF to I2S). Connect a Wavefront (used to be Alesis Semiconductor) AL1401A to the four recovered streams, delayed (if required) to a common bit clock, a Toslink transmitter (TOTX173 I guess) and you're done. So ADAT output is simple and cheap.

I suppose the ADAT input would be trickier. First, you've got to receive the optical with a TORX173, then demux it by an AL1402. A conversion to S/PDIF for the first four channels is easy (even in general purpose logic). Now, the problem is that the I2S inputs require a slave at the other side. If the Emu10k2 can be slaved to the S/PDIF clock, it's no problem, since all ADAT channels have a common clock, and all that is needed is simple delaying of samples to achieve synchronisation with the I2S sample sync signal. However, if the Emu10k2 is persistent in keeping its own clock, it's very bad, because resampling will be needed and it's not like it's easy, because the two clocks will be very close and will probably float with temperature .

I've got all the chips lying around in here, so it's a matter of designing a PCB and the FPGA logic for standard conversion and retiming.

How do you think, does it make sense? I don't know a lot about Emu10k (although I do know a bit about ADAT - I have done some experiments with my SGI Octane which has ADAT built in and with the Alesis chips, too - I'm writing a reverse-engineered audio driver for it so I need some ADAT reference). BTW. This is a good audio implementation, you can slave any clock to any clock in it.
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Old Aug 26, 2004, 09:40 AM   #2
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Thumbs Up!

(Travelrec will know a *LOT* more than me on this topic, but here's a start...)

If you simply plug a SPDIF source into one of the SPDIF pins on AUD_EXT, the EMU10K2 will, by default, resample that SPDIF input to its own 48khz clock on-the-fly. So, there can be a small loss of quality. However, in recent kX driver revisions, something called "SPDIF Bypass" allows you to record one of the SPDIF inputs *without* resampling--but at the moment, it's limited to use with the WinMM recording, so only 2 channels can be recorded at a time.

If alll your sources were guaranteed to be the same clock rate, I can't think of a reason you couldn't SPDIF bypass four channels and I2S four channels (I could be wrong, but I don't think I2S resamples either) and then let Eugene modify the driver to allow bypassed channels to go to ASIO...

I think this is possible! Keep us posted on what happens with it!
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Old Aug 26, 2004, 10:33 AM   #3
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??? I2S woes

S/PDIF would work, it's clear. Now, the I2S might be a problem.

Who is the master of I2S - in other words, who generates the Frame Sync and Bit Clock (especially the Bit Clock)? Because if it's not the add-on, there *will* be some serious problems with resampling. I looked around a bit and resampling frequencies that are close (47.9998 kHz -> 48.0012 kHz for instance) is pretty impossible.

Of course, the easiest way would be to repeat or drop samples when the clocks slip, but this would be so ugly I'm not having anything like that here...

It is a pity that the card clock can't be slaved to one of the S/PDIFs. I mean, it's not like it's hard, it's just a single PLL to up-convert the input clock to some convenient frequency and a clock multiplexer.
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Old Aug 26, 2004, 10:58 AM   #4
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well if you're ambitious enough to make your own PCBs, you probably have a soldering iron that's studly enough you could make your own clock circuits for your card... I think the pins on the 10K2 chip for clock sync and everything are known, and it sounds like you'd know enough to perform the modification...

http://www.electricstart.de/index.htm

Travelrec is, IMO, the most knowledgeable about these things--he's in Germany, so he'll maybe see this thread and reply while we're sleeping tonight.
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Old Aug 26, 2004, 11:39 AM   #5
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Unfortunately the I2S master is really the Emu10k2 chip.

I think there is one crystal on the Audigy2. So it's probably 24.576 MHz for the whole card. I would probably find out which pin is the input, which is the output and solder something to the input. This should allow me to clock the card at will. This is not the end of troubles, though.

The Alesis AL1402 receiver has only a 12.288 MHz output so I'd have to double the frequency.

There is also a question of switching from internal crystal to ADAT and back. After all, we don't want the card to work only if an ADAT input is connected to it, and hang the machine if it isn't. (Which would probably happen.)

This will be a real problem because exceedingly assymetrical clock cycles (which would appear during a switch) can upset digital logic badly, especially if it uses PLLs (which it surely does, to generate the 98.304 MHz core clock). More often than not, the aforementioned logic would have to be reset.

So it would be needed to make a phase-aligned switch (switch from one clock to another when the phase difference between them is small). This is no mean feat, especially if clocks are very close and the phase-alignment seldom happens (as it is the case here - it might never happen, too).

It is possible that a smooth transition between two clocks could be done using a PLL retimer with a long adaptation time. However, PLLs exhibit interesting non-linear properties, which essentially means that we don't know until we test it
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Old Aug 26, 2004, 03:24 PM   #6
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System Specs

the audigy series cards can slave to an external clock
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Old Aug 26, 2004, 04:44 PM   #7
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Where should I apply this clock?
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Old Aug 26, 2004, 04:57 PM   #8
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System Specs

i'm not sure how… otherwise you could try to use the ac97 clock and halve it
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Old Aug 26, 2004, 05:04 PM   #9
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No way I can use the AC97 clock. The AL1402 is the ADAT receiver and it's always synchronous to the incoming ADAT clock. It is "emu10k, use my clock or DIE!".
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Old Aug 27, 2004, 01:19 AM   #10
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Hi thesis!

On Audigy 2 cards the I2S seems to be a master device. You´ll get the bitclock from the card. Ask user SAMIR for the complete layout of AD_EXT. He´s the one who figured out the pinout . But all these is not really tested yet. A possible way to do what you want, is to resample that signals before feeding in I2S (i´ve done this for my Audigy1 with a Sample Rate Converter from Crystal: CS8420, very cool S/N performance -112db), this helps to avoid clicking and desyncronizing, due to the locked DSP. BTW: I have 14 input channels with the Audigy 1 (with AC97), with Audigy 2 you can get 12 if you use Philips onboard 2nd A/D and AC97 too.

Greetings!

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Old Aug 27, 2004, 02:07 AM   #11
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Hi, and thanks for the authoritative reply!

I think that it would be better to slave the board clock to my clock. It would mean better quality, and I think it could be done. What would be needed is to add a retimer after the ADAT clock. This will be a PLL to lock on the input signal. There are two possible realizations:

* a typical VCO-based PLL that would be switched from ADAT clock to internal clock
* a VCXO-based PLL that would be synchronized to ADAT clock or free-running

The first approach is easier, but the second one provides better jitter and other timing properties, too - the ADAT clock is "cleaned" from jitter by the inherently low-jitter VCXO (telecommunications systems tend to use VCXO here-and-there for this very purpose). However, the question of VCXO pullability (they are crystal-based so they don't change a lot even if you want them to) requires some experiments.
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Old Sep 1, 2004, 01:45 AM   #12
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Hi again!

You are on the right way. One reason why I suggested the CS8420 is, that it has 2 different stages: one PLL input stage that has high jitter rejection, and the output stage that can easily read out with soundcard´s clock. Samplerate ratio can vary between 1:3 and 3:1. Chip´s performance is also cool (like I said) and it runs in hardware-mode (without the need of any processor). I think, it´s possible to add two of such devices (one Master, one Slave) on I2S port. Slaving the I2S is not possible - and if you use SRCs there is no need of it.

Greetings!

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Old Sep 6, 2004, 04:46 PM   #13
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OK, so I'm reclocking the whole card. AFAIR there is one 24.576MHz crystal. If I dike it out and feed the card with my own 24.576MHz (plus or minus a few ppm), I'll have my way without resampling (it wouldn't be bit-accurate; why use ADAT if you are not bit-accurate anyway?).

I think I will use a high-stability TCXO at 100 MHz and clock a AD9850 digital clock synthesizer from it. The clock synth is nice because I can give it a 32-bit word and it gives me the *exact* frequency I wanted. This clock will be lowpass-filtered so no harmonics will come and jitter it around. The output will be fed into the card.

The tuning of the AD9850 will be done using a phase-frequency detector and a small microcontroller (ADuC814 for instance). This should solve the problem of wander. If there is an ADAT input clock, the card will be slowly (at least a few seconds) drift to the ADAT clock, and then phase-lock with it. If there is no ADAT clock, the microcontroller will keep the last used frequency.
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Old Sep 7, 2004, 01:31 AM   #14
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Hi!

Sounds cool, if it is working, please let us know . But don´t burn your card - I don´t know, how the 10k2 will react on false main frequency input (if an error creates higher clocks than specified...). It´s nice to see what people do to get maximum power from their "consumer" sound-cards .

Good luck!

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Old Sep 9, 2004, 08:18 AM   #15
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thesis:

Maybe this info might help you.... It shows how clock crystal is connected to the rest of the card trought p16v chip which seems to control other chip's clocks...

http://www.bih.net.ba/~info.com/Audi...ngineering.gif

Keep up the good work & keep us posted about your progres...
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Old Sep 11, 2004, 03:00 AM   #16
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Thanks, it was very useful.

BTW. I am in the power to start a small-scale production of something like this. I estimate the price to be about $150 for the end-user. Of course, the schematics and code will be still available on the net, but the difficulty in gathering all the parts and soldering the 0.5mm raster chips is considerable (and the cost of setting up a PCB fabrication at this quality level is high, too).

The question is, would anybody be interested in it?
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Old Sep 11, 2004, 12:03 PM   #17
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If all it does is ADAT, I would not be interested. I am thinking about a breakout box for my card though.

I need a box that will give me every possible analog input and output for my card with a reasonably good SNR--though if you can beat 96dB, that's a good thing. :-) For my needs, I'd also need at least two pairs of analog inputs to be able to switch to SPDIF so I can record things from my SPDIF-enabled CD players. If this box had ADAT i/o support on top of that, I'd be happy to pay extra for that--after all, maybe someday I'll have to transcribe things from ADAT or something...
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Old Sep 11, 2004, 01:23 PM   #18
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Sad

Most of the difficulty lies in making bit-accurate digital inputs. So if you want just another analog input, I think you can do it much easier with a PCM1804 from Burr-Brown (now TI), which has really good performance (111 dB SNR, -102 dB THD+N - it is almost unbelievable). In this case the card can clock the chip, so there is no question of reclocking the card and stream synchronization.

And the PCM1804 chip itself costs about $5 in large quantites. So expect no more than $10 in small quantities . No point in making a very expensive reclocking breakout box for $10.

What we could do, is a digital breakout box (an 8-channel synchronized ADAT output plus four S/P-DIF outputs straight from the card) - this part is easy - and an 8-channel synchronized clock-locking ADAT input or four S/P-DIF inputs (one with a resampler), clock-locking. Note that all S/P-DIF inputs but one could be bit-accurate (two physical S/P-DIF inputs - S/P-DIF-0-in on AD-EXT and S/P-DIF-CD-in and one I2S clock-locking so inherently bit accurate, too). Adding an analog board to this can be done, too, but if the whole point is using analog then there is no gain in doing something like this.

Yours,

Stanislaw Skowronek
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Old Sep 11, 2004, 03:35 PM   #19
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Quote:
What we could do, is a digital breakout box (an 8-channel synchronized ADAT output plus four S/P-DIF outputs straight from the card) - this part is easy - and an 8-channel synchronized clock-locking ADAT input or four S/P-DIF inputs (one with a resampler), clock-locking. Note that all S/P-DIF inputs but one could be bit-accurate (two physical S/P-DIF inputs - S/P-DIF-0-in on AD-EXT and S/P-DIF-CD-in and one I2S clock-locking so inherently bit accurate, too).
Exactly what I was thinking.

Quote:
Adding an analog board to this can be done, too, but if the whole point is using analog then there is no gain in doing something like this.
No gain? I disagree! -Right now-, I need more analog ins and outs; but I also need more than 1 SPDIF input that takes external-level signals, and someday I might need ADAT support--it's worth the extra cost and complexity to me, to have that option down the road.

The other complicating factor is that I am not an electronics guru, but you are. (Also Travelrec.) I don't think I made this clear earlier, but I'd much rather pay someone else to build this box for me, than to try to build it myself. (Unless it'd be less expensive to just buy a Dakota and name-brand outboard AD/DA box... I find that scenario unlikely.)
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Old Mar 31, 2009, 08:47 PM   #20
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Re: Adding ADAT support to Audigy2

Help! H-SPHERE is a dead link! Does anyone have a cached copy of it? I can host if. I'm attempting to sync some EMU10K cards (Audigy 2 ZS as master,arbitrary slaves) to the same clock. Since pin 13 of AD_EXT (P16VCLK) outputs a 24.576 MHz clock, can I simply pull off X2 (24.576HC2B) from the slave card(s) and use a simple buffer circuit to clock it to the master card? What would such circuitry look like? If I understand correctly, a PLL wouldn't be needed, since the master clock is exactly the desired frequency.
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Old Apr 1, 2009, 02:22 AM   #21
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Re: Adding ADAT support to Audigy2

Best way is to desolder the crystals on the slave cards and route the P16VClock to all slave cards on XTAL1. Insert a 33 Ohm series resistor on each wire. Keep the wires as short as possible or take shielded wires.
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Old Apr 1, 2009, 03:11 PM   #22
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Re: Adding ADAT support to Audigy2

Should I tie VSS (chip ground) together on the cards? How about PLLVSS? Should I connect my P16VCLK to XI through a 33ohm resistor and let XO float?

How much current do you think P16VCLK can source? How much do you think the EMU10Ks sink? In other words, how many additional cards can I run off of P16VCLK? Would I be better off daisychaining the other cards using CLK24MHz_Out (not all the cards have P16Vs)?

From a pinout i found somewhere:

Quote:
127 PLLVDD (PLL Power)
128 XO (Crystal Oscillator output)
129 PLLVSS (PLL Ground)
130 XI (24.576 MHz Clock from Oscillator or crystal)
131 VDD
...
174 CLK24MHz_Out (Buffered Clk 512, Approx.24.576MHz. Same as crystal)
The entire pinout document:
Quote:
Pin outs for the Audigy2 chips.
E.g. CA0108, CA10300 etc.

Left
1 IN_MIDI_A
2 SDA0
3 SL0
4 SCS
5 SCLK
6 VSS (Chip ground)
7 SDA
8 SDAIN
9 JOY_CMP0 (analog)
10 JOY_CMP1 (analog)
11 JOY_CMP2 (analog)
12 JOY_CMP3 (analog)
13 VDD (Chip power 1.8V)
14 JOYPB0 (switch pull-up)
15 JOYPB1 (switch pull-up)
16 VDDIO (IO power 3.3V)
17 VSS (Chip ground)
18 JOYPB2 (switch pull-up)
19 JOYPB3 (switch pull-up)
20 JOY_TRIGN (Output)
21 VDD (Chip power 1.8V)
22 INTAN (PCI Interrupt active low)
23 PCIRSTN (PCI bus reset IN)
24 VSS
25 PCICLK (PCI bus clock IN)
26 GNTN (PCI bus grant not IN)
27 VDDIO (IO power 3.3V)
28 REQN (PCI request not OUT)
29 AD31 (PCI addr)
30 AD30
31 VSS
32 AD29
33 AD28
34 AD27
35 VIO5V (Pads biasing 5V)
36 AD26
37 AD25
38 AD24
39 VSS
40 CBEN3 (PCI command byte enable)
41 IDSEL (PCI device select for configuration)
42 AD23
43 VDD
44 AD22

Bottom
45 AD21
46 AD20
47 AD19
48 VSS
49 AD18
50 AD17
51 AD16
52 CBEN2 (PCI command byte enable)
53 FRAMEN (PCI frame, active low)
54 VDDIO
55 IRDYN (PCI Initiator Read Signal, Active low)
56 TRDYN (PCI Target Ready, Active low)
57 DEVSELN (PCI Target Device Select Not)
58 STOPN (PCI STOP Transfer Control Signal, Active low)
59 PERRN (PCI Parity Error Report Signal. Active low)
60 VSS
61 SERRN (PCI System Error Report, Active low)
62 PAR (PCI Bus Parity)
63 CBEN1 (PCI command byte enable)
64 VDD
65 AD15
66 VIO5V
67 AD14
68 AD13
69 AD12
70 AD11
71 VSS
72 AD10
73 AD9
74 AD8
75 CBEN0
76 VDDIO
77 AD7
78 AD6
79 AD5
80 AD4
81 VSS
82 AD3
83 AD2
84 AD1
85 VDD
86 AD0
87 VIO5V
88 SCANCLK (In)

Right
89 SCANEN (In pull-down)
90 EESDO/I2C_SDA (Serial Host Data to EEPROM, Out )
91 VSS
92 EESDI (In)
93 EECLK/I2C_SC (EEPROM Interface Bit Clock, Out)
94 EECS (Out)
95 EE_Sel (EEPROM Select)
96 E32FSON (Out)
97 VDDIO
98 E32IND1 (In)
99 E32IND0 (In)
100 E32OBC (Out)
101 E32OD1 (Out)
102 VSS
103 E32OD0 (Out)
104 E32OCCN (Out)
105 MFSIN (In)
106 I2SINLR0 (Left Right for I2S Input, Bi-directional)
107 I2SINBCLK0 (Bit Clocks for I2S Input, Bi-directional)
108 VDD
109 I2SIN0 (In)
110 GPI0 (General Purpose input)
111 IN_MIDI_B
112 OUT_MIDI_B
113 VDDIO
114 GPI1 (General Purpose input)
115 SPDIFO2 (SPDIF Output)
116 VSS
117 SPDIFO1 (SPDIF Output)
118 SPDIFO0 (SPDIF Output)
119 SPDIFO3 (SPDIF Output)
120 GPO0 (General Purpose output)
121 GPO1 (General Purpose output)
122 VSS
123 GPO2 (General Purpose output)
124 SPDIFIB (SPDIF Input)
125 VOL_INC_N (In)
126 VOL_DEC_N (In)
127 PLLVDD (PLL Power)
128 XO (Crystal Oscillator output)
129 PLLVSS (PLL Ground)
130 XI (24.576 MHz Clock from Oscillator or crystal)
131 VDD
132 SPDIFIC (SPDIF Input)

Top
133 SPDIFIA (SPDIF Input)
134 GPI2 (General Purpose input)
135 I2SIN2 (Data In)
136 I2SINBCLK2 (Bit Clocks for I2S Input, Bi-directional)
137 VSS
138 I2SINLR2 (Left Right for I2S Input, Bi-directional)
139 I2SIN1 (Data In)
140 I2SINBCLK1 (Bit Clocks for I2S Input, Bi-directional)
141 VDDIO
142 I2SINLR1
143 I2SIN_MCLK (Master Clock for I2SIN ADC)
144 GPI3
145 VSS
146 GPI4
147 B_RESET (Out)
148 IDDQPC (Input)
149 GPI5
150 VDD
151 GPO3
152 GPO4
153 GPO5
154 GPO6
155 VSS
156 IRIN (In, Pull-up)
157 TEST (In, Pull-down)
158 GPO7
159 I2SOUTBCLK (Bit Clocks for I2S Output, Bi-directional)
160 I2SOUTLRCLK (Left Right for I2S Output, Bi-directional)
161 I2SOUT0 (Data out)
162 I2SOUT1 (Data out)
163 VSS
164 I2SOUT2 (Data out)
165 I2SOUT3 (Data out)
166 CLK256FS (256 * Sample Rate Output)
167 VDDIO
168 AC97SYNC (Sync Output to AC97 CODEC)
169 AC97BCK (AC97 Bit Clock)
170 VSS
171 AC97SDI (Serial Data Input from AC97 CODEC)
172 AC97SDO (Serial Data Output to AC97 CODEC)
173 AC97RSTN (Reset Not to AC97 CODEC, Output)
174 CLK24MHz_Out (Buffered Clk 512, Approx.24.576MHz. Same as crystal)
175 VDD
176 OUT_MIDI_A
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Old Apr 1, 2009, 03:38 PM   #23
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Re: Adding ADAT support to Audigy2

Uuuh - from where you got the complete pinout of the 10k2? I´m recently figured most of them out from scratch - damn...
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Last edited by TravelRec.; Apr 2, 2009 at 12:23 AM.
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Old Apr 1, 2009, 05:24 PM   #24
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Re: Adding ADAT support to Audigy2

I was wondering the same thing TravelRec.......... confirming the CA10300 is the same pinout too....... Nice!
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Old Apr 1, 2009, 08:58 PM   #25
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Re: Adding ADAT support to Audigy2

TravelRec (or anyone else), can you answer any of my questions?
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Should I tie VSS (chip ground) together on the cards? How about PLLVSS? Should I connect my P16VCLK to XI through a 33ohm resistor and let XO float?

How much current do you think P16VCLK can source? How much do you think the EMU10Ks sink? In other words, how many additional cards can I run off of P16VCLK? Would I be better off daisychaining the other cards using CLK24MHz_Out (not all the cards have P16Vs)?
By the way, I have a dead SB0090 that I plan to trace visually (by desoldering components that cover traces) and with a multimeter. I don't have an oscope, so i cant do much more than that i dont think. any ideas/requests?
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Old Apr 1, 2009, 09:01 PM   #26
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Re: Adding ADAT support to Audigy2

Oh, and I got that pinout from http://alsa.cybermirror.org/manuals/...digy2-pins.txt
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Old Apr 2, 2009, 12:33 AM   #27
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Re: Adding ADAT support to Audigy2

chipwizme: You must not connect GND of the different cards together, this is done by the PCI socket. Then you should use the buffered clock output as clock master for the other cards. Route this line through the resistor(s) to XI on the other cards. Leave XO open. I think, thats it. The clock output should source 2-3 mA, the XI is a CMOS input which has only some pF input capacitance and only some µA input leakage current. The cable to connect all clock inputs is more critical. If there is an external resistor between XI and XO on the clock slaves, it should be removed.

BTW: Thanks for the pinout. This helps to get all out of the value card versions where most of the features of the chipset are not used but available
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