Zardon

Yes, I had to put on an airconditioner with both it and the IntelV8 running. The test room got really warm without it. With the side panel off, you could really feel the heat escaping - a portion of this however did come from the graphics cards.

Also with regards to the watercooling, I have to say those Corsair Nautilus 500's for an entry level "all in one" configuration do a fine job, however after 3 or 4 hours gaming the water got rather warm (at 4.2ghz with the higher voltage), they still coped admirably though. I am sure however that someone thinking of buying this system would invest in a high end configuration costing 3 times as much. Load temperatures would probably drop a further 5-10c.

All in all though, I have to stress just how rock solid the platform is. Just like the Intel V8 system these machines rarely, if ever BSOD. I think the Intel V8 has BSOD'd ONCE in a year, which I put down to a beta set of drivers. I have yet to see the Skulltrail doing it. Perhaps the fully buffered memory has a bit of a hand in this.

For those interested in the whole fully buffered memory deal there are plenty of great reads about it on the internet and a good place to start is the wikipedia pages.

"Fully Buffered DIMM architecture introduces an Advanced Memory Buffer (AMB) between the memory controller and the memory module. Unlike the parallel bus architecture of traditional DRAMs, an FB-DIMM has a serial interface between the memory controller and the AMB. This enables an increase to the width of the memory without increasing the pin count of the memory controller beyond a feasible level. With this architecture, the memory controller does not write to the memory module directly, rather it is done via the AMB. The AMB can thus compensate for signal deterioration by buffering and resending the signal. In addition, the AMB can also offer error correction, without posing any overhead on the processor or the memory controller. It can also use the Bit Lane Failover Correction feature to identify bad data paths and remove them from operation, which dramatically reduces command/address errors. Also, since reads and writes are buffered, they can be done in parallel by the memory controller. This allows simpler interconnects, more memory bandwidth, and (in theory) hardware-agnostic memory controller chips (such as DDR2 and DDR3) which can be used interchangeably. The downside to this approach is that it introduces latency to the memory request."

Will be interesting to see how this story develops over the coming months......